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POWER9 - LaGrange Module
Based on IBM® Power Architecture®, IBM POWER9 systems target technical computing segments by providing superior floating-point performance and off-chip floating-point acceleration. POWER9 systems, which consist of superscalar multiprocessors that are massively multithreaded, support Cloud operating environments. With the Coherent Accelerator Processor Interface (CAPI) attached, POWER9 systems offer a robust platform for analytics and big data applications.
The POWER9 LaGrange module has the following key characteristics: 68.5 mm x 68.5 mm, FC-PLGA, 8 DDR4, 42 PCIe Lanes and 2 XBus 4B
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POWER9 Workshop Material
Worskhop based material beneficial to those developing around POWER9.
System Test and Compiler Videos (Group 2 of 2) from Beijing & Taipei POWER9 Developer ForumsThis posting includes the Group 2 videos of the System Test & Compiler portion of the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The System Test & Compiler Group 2 videos cover: POWER9 RAS & Getting Your Applications Ready for IBM POWER9 - Use latest Compiler technology to explore P9 functionality.
Read More & Download | Provide Feedback | Share | Revision Date: 06/29/2017
Overview Videos (Group 2 of 2) from Beijing & Taipei POWER9 Developer ForumsThis posting includes the Group 2 videos of the Overview portion of the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The Overview Group 2 videos cover: OCC, Power and Thermal
Read More & Download | Provide Feedback | Share | Revision Date: 06/29/2017
Hardware Videos from Beijing & Taipei POWER9 Developer ForumsThis posting includes videos of the Hardware portion of the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The Hardware videos cover: 25G Link, PCIe Design, DC-DC Power Design and Validation for POWER9, & IBM POWER9 IBIS-AMI Models for OpenPOWER.
Read More & Download | Provide Feedback | Share | Revision Date: 06/27/2017
Firmware Videos (Group 1 of 2) from Beijing & Taipei POWER9 Developer ForumsThis posting includes the Group 1 videos of the Firmware portion of the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The Firmware Group 1 videos cover: POWER9 Firmware and Initialization & Opal and Linux.
Read More & Download | Provide Feedback | Share | Revision Date: 06/27/2017
Firmware Videos (Group 2 of 2) from Beijing & Taipei POWER9 Developer ForumsThis posting includes the Group 2 videos of the Firmware portion of the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The Firmware Group 2 videos cover: Secure and Trusted Boot with TPM & the OpenBMC Introduction.
Read More & Download | Provide Feedback | Share | Revision Date: 06/27/2017
System Test and Compiler Videos (Group 1 of 2) from Beijing & Taipei POWER9 Developer ForumsThis posting includes the Group 1 videos of the System Test & Compiler portion of the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The System Test & Compiler Group 1 videos cover: X-bus Verification Process, PCIe Verification Process, DDR4 Memory Subsystem Verification, & POWER9 System Test.
Read More & Download | Provide Feedback | Share | Revision Date: 06/27/2017
Overview Videos (Group 1 of 2) from Beijing & Taipei POWER9 Developer ForumsThis posting includes the Group 1 videos of the Overview portion of the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The Overview Group 1 videos cover: POWER9 Architecture , OpenCAPI, POWER9 Performance, & the IBM Portal for OpenPOWER.
Read More & Download | Provide Feedback | Share | Revision Date: 06/27/2017
Hardware Documents from Beijing & Taipei POWER9 Developer ForumsThis posting includes 4 various Hardware documents shown at the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The 4 Hardware documents cover: 25G Link PCIe Design DC-DC Power Design and Validation for POWER9 IBM POWER9 IBIS-AMI Models for OpenPOWER
Read More & Download | Provide Feedback | Share | Revision Date: 06/16/2017
System Test and Compiler Documents from Beijing & Taipei POWER9 Developer ForumsThis posting includes 5 various System Test & Compiler documents shown at the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The 5 System Test & Compiler documents cover: X-bus Verification Process PCIe Verification Process DDR4 Memory Subsystem Verification POWER9 System Test and RAS Getting Your Applications Ready for IBM...
Read More & Download | Provide Feedback | Share | Revision Date: 06/16/2017
Overview Documents from Beijing & Taipei POWER9 Developer ForumsThis posting includes 5 various Overview documents shown at the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The 5 Overview documents cover: POWER9 Architecture OpenCAPI POWER9 Performance OCC, Power & Thermal IBM Portal for OpenPOWER
Read More & Download | Provide Feedback | Share | Revision Date: 06/16/2017
Firmware Documents from Beijing & Taipei POWER9 Developer ForumsThis posting includes 4 various firmware documents shown at the June'17 POWER9 Developer Forums in Beijing, China & Taipei, Taiwan. The 4 firmware documents cover: POWER9 Firmware and Initialization Opal and Linux Secure and Trusted Boot with TPM OpenBMC Introduction
Read More & Download | Provide Feedback | Share | Revision Date: 06/16/2017
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POWER9 System Design - LaGrange Module
System designers can use this material to develop systems that make effective use of IBM® POWER9 components, modules, and interfaces. The information provided relates to power and thermal requirements, hardware validation, design rules, and the memory subsystem.
The POWER9 LaGrange module has the following key characteristics: 68.5mm x 68.5mm, FC-PLGA, 8 DDR4, 42 PCIe Lanes and 2 XBus 4B
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System Test (POWER9 LaGrange)
These documents describe the recommendations for testing and verifying an IBM® POWER9™ system.
POWER9 Systems RAS Test GuideThis document describes how to use IBM® tools to verify that reliability, availability, and serviceability (RAS) functions are working correctly in an OpenPOWER POWER9 system. These tools inject errors into a system for RAS testing.
Read More & Download | Provide Feedback | Share | Revision Date: 10/10/2018
Hardware System Test GuideThis document describes how to use the IBM® Hardware Test Executive (HTX) and other tools to validate the hardware design of IBM Power Systems™. The HTX is a suite of test tools that IBM validation labs use during processor bring-up, hardware system integration, I/O verification (IOV), characterization, and manufacturing. This document...
Read More & Download | Provide Feedback | Share | Revision Date: 10/17/2017
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System Firmware (POWER9 LaGrange)
These links and documentation provide details related to the System Firmware in support of designing an IBM® POWER9 system with the POWER9 Processor - LaGrange Module.
OpenPOWER Firmware DocumentationThis link takes you to the OpenPOWER Firmware Documentation Repository on GitHub. The repository contains documentation for the OpenPOWER open source firmware that's being released to support the POWER ecosystem.
Read More & Download | Provide Feedback | Share | Revision Date: 10/05/2015
OpenPOWER Firmware Training VideosThe OpenPOWER Firmware Training Videos are a series containing information about the Firmware IBM donated to the OpenPOWER Foundation. This series of videos should serve as a fast way to understand the concepts and get to real development faster. See read me file for details of material provided and sequence for use.
Read More & Download | Provide Feedback | Share | Revision Date: 06/16/2015
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Reference Design Examples (POWER9 LaGrange)
These reference designs describe the essential components of an IBM® POWER9 system with the POWER9 Processor - LaGrange Module.. Third parties may copy, enhance, and modify these designs. Use of these designs enables engineers to quickly evaluate systems and may reduce product development time.
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TPM Riser Card (LaGrange)
This material supports Trusted Platform Module (TPM) riser card designs with the POWER9 processor LaGrange module.
Trusted Platform Module Riser Card DesignThe specialized schematic and layout files provided here support the OpenPOWER Trusted Platform Module (TPM) riser card design. Used with EDA software from Cadence Design Systems, Inc., these files enable the efficient design of PCBs for the TPM riser card design. This riser card can be used in IBM POWER8, IBM POWER8 with NVIDIA® NVLink™...
Read More & Download | Provide Feedback | Share | Revision Date: 02/14/2018
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2-Socket Reference Design (LaGrange)
This material supports 2-socket IBM® POWER9 designs with the POWER9 Processor - LaGrange Module.
Zaius / Barreleye G2 Reference Design (Open Compute Project)The Zaius / Barreleye G2 Reference Design describes the specifications for: Zaius POWER9 motherboard Barreleye G2 server Zaius server Zaius and Barreleye G2 are OpenPOWER-based Open Compute servers, based upon a common Zaius motherboard specification. These servers have mechanical and electrical packages designed for the 48-volt Open Rack v2. The...
Read More & Download | Provide Feedback | Share | Revision Date: 12/07/2016
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Programmable Components (POWER9 LaGrange)
Many components of an IBM® POWER9 system are programmable. These documents describe the required components and how to acquire them. Where appropriate, they also describe how to program the components.
POWER9 Programmable Components Readme FileThis document lists the programmable components needed for an OpenPOWER IBM® POWER9™ system. It explains what components are needed, how to procure the components, and where appropriate, how to program them. The compressed file named P9_eATX_PPL_rev1.zip (POWER9 Programmable Components List, Revision 1.0) is used in conjunction with this...
Read More & Download | Provide Feedback | Share | Revision Date: 09/29/2017
Vital Product Data Records for POWER9 Scale Out Field Replaceable Units User's GuideThis document explains how to create vital product data (VPD) records for OpenPOWER field replaceable unit (FRU) cards. The FRU VPD contains information describing the card assembly. It contains the part number and serial number of the FRU, the manufacturer of the FRU, and more. In some instances, the FRU VPD contains data that is used to initialize...
Read More & Download | Provide Feedback | Share | Revision Date: 09/05/2017
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Mechanical and Thermal (POWER9 LaGrange)
These documents describe mechanical and thermal features of an IBM® POWER9 system with the POWER9 Processor - LaGrange Module.
POWER9 Thermal and Mechanical Reference Guide for the LaGrange SCMThis reference guide provides the mechanical and packaging specification for the IBM® POWER9™ processor. It describes the thermal modeling of the POWER9 processor and the memory subsystem.
Read More & Download | Provide Feedback | Share | Revision Date: 08/21/2019
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Design Guidelines (POWER9 LaGrange)
These documents describe the recommendations, rules, and requirements for designing an IBM® POWER9 system with the POWER9 Processor - LaGrange Module
POWER9 LaGrange Platform Design GuideThe IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It supports direct-attach memory and a maximum symmetric multiprocessing (SMP) size of two sockets. It is targeted for scale-out workloads. Topics covered in the design guide include: The power delivery system ...
Read More & Download | Provide Feedback | Share | Revision Date: 11/27/2018
POWER9 LaGrange Single-Chip Module (SCM) Schematic ChecklistThe IBM® POWER9™ LaGrange SCM schematic checklist is a spreadsheet containing the rules for processor logical connectivity in a one- or two-socket system. Its purpose is to describe direct connections to and between the processors that are necessary for proper function. Fill out this checklist before requesting a logic review from IBM,...
Read More & Download | Provide Feedback | Share | Revision Date: 11/07/2018
POWER9 Memory Subsystem for DDR4 IS RDIMMs Validation GuideThis document covers the following aspects of the OpenPOWER memory subsystem: Power-on Bring-up Characterization Reliability, Availability and Serviceability (RAS) Power, Thermal, and Performance Dual in-line memory module (DIMM) Supplier Qualification for the OpenPOWER platform
Read More & Download | Provide Feedback | Share | Revision Date: 10/23/2018
POWER9 PCIe Controller Functional SpecificationThis document describes the design and operation of the IBM® POWER9™ PCI Express Controller (PEC). It provides details on its basic requirements, function, operation, and usage. It serves as a reference document for designers, simulators, testers, and programmers. The following link will take you to POWER9 PCIe Controller Fuctional Specification: ...
Read More & Download | Provide Feedback | Share | Revision Date: 07/27/2018
Power Systems Host Bridge 4 (PHB4) SpecificationThis document describes the design and operation of the IBM® Power Systems™ Host Bridge 4 (PHB4) building block. It provides information on the requirements, function, operation, and usage. The following link will take you to POWER Systems Host Bridge 4 (PHB4) Specification: POWER Systems Host Bridge 4 (PHB4) Specification
Read More & Download | Provide Feedback | Share | Revision Date: 07/27/2018
POWER9 LaGrange Single-Chip Module (SCM) Layout ChecklistThe IBM® POWER9™ LaGrange SCM layout checklist is a spreadsheet containing the rules for the PCB design of a POWER9 SCM planar. Its purpose is to describe layout rules for miscellaneous nets, high-speed buses, and power integrity that are necessary for proper function. It is recommended that this checklist be reviewed prior to layout,...
Read More & Download | Provide Feedback | Share | Revision Date: 07/16/2018
POWER9 Systems Power Validation and Test GuideThis document describes how to perform power-integrity related checks of a system designed with the IBM POWER9 processor technology. All the tools and procedures described in this document are examples. System designers are free to supplement these procedures with their own.
Read More & Download | Provide Feedback | Share | Revision Date: 06/20/2018
IBM Methodology for Adding Signal-Integrity Guidelines for High-Speed Interconnections to the Cadence Allegro Constraint ManagerThis document describes the methodology used to add IBM® signal integrity (SI) guidelines for OpenPOWER systems into the Cadence Allegro 16.5 Constraint Manager for the PCIe and DMI buses. It includes the following information: An example of SI guidelines used in the document A description of the CSet rules nomenclature Guidelines for creating...
Read More & Download | Provide Feedback | Share | Revision Date: 10/04/2017
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POWER9 Processor - LaGrange Module
The IBM® POWER9 processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. The POWER9 processor uses 14 nm technology with 17 metal layers. It supports direct-attach memory and provides superior floating-point performance and high memory bandwidth.
The POWER9 LaGrange module has the following key characteristics: 68.5 mm x 68.5 mm, FC-PLGA, 8 DDR4, 42 PCIe lanes and 2 XBus 4B.
POWER9 LaGrange Single-Chip Module DatasheetThis datasheet describes the IBM® POWER9™ processor. The POWER9 processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It uses 14 nm technology with 17 metal layers. The POWER9 processor can have up to 24 cores enabled on a single chip. It supports direct-attach memory and a maximum...
Read More & Download | Provide Feedback | Share | Revision Date: 07/31/2020
POWER9 Processor User's ManualThe link below will take you to the POWER9 Processor User's Manual: POWER9 Processor User's Manual The IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It uses 14 nm technology with 17 metal layers. The POWER9 processor supports direct-attach memory. It supports...
Read More & Download | Provide Feedback | Share | Revision Date: 10/10/2019
POWER9 Processor SCM Hardware Errata Notice DD 2.2This document describes known errata applicable to IBM® POWER9™ processor single-chip module (SCM) devices as well as any workarounds. An erratum is identified if the actual operation differs from the system design described in the POWER9 User Manuals and Datasheets. Each erratum is assigned to a category based on its impact on system...
Read More & Download | Provide Feedback | Share | Revision Date: 04/19/2019
POWER9 Performance Monitor Unit User’s GuidePerformance instrumentation is divided into two broad categories: the performance monitor and the trace facilities. The IBM POWER9 chip has built-in features for monitoring and collecting data for performance analysis. Collectively, the features are referred to as instrumentation. This document provides a user’s view of the POWER9 hardware...
Read More & Download | Provide Feedback | Share | Revision Date: 04/18/2019
POWER9 Power Systems Secure BootThis document provides specifications and requirements for how to preform a Secure Boot with the IBM® POWER9™ systems.
Read More & Download | Provide Feedback | Share | Revision Date: 08/10/2018
POWER9 Processor Registers SpecificationThe links below will take you to the POWER9 Processor Registers Specification POWER9 Processor Registers Specification, Volume 1 POWER9 Processor Registers Specification, Volume 2 POWER9 Processor Registers Specification, Volume 3 The IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and...
Read More & Download | Provide Feedback | Share | Revision Date: 05/08/2017
POWER9 Memory IBIS ModelThe input/output buffer information specification (IBIS) models for IBM® POWER9™ DDR4 memory provide information about the characteristics of the pins associated with this product. Developers can use this information to include the POWER9 DDR memory in their simulations.
Read More & Download | Provide Feedback | Share | Revision Date: 07/29/2016
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POWER9 Miscellaneous Material - LaGrange Module
This material is POWER9 Processor - LaGrange Module miscellaneous material.
POWER9 Processor Programming Guide for the 25G Link with NVLink 2.0 Compliant DevicesThe IBM® POWER9™ chip includes the high-speed 25G Link, which creates an interface between chips that provides both cache coherence and very high data bandwidth. For example, this structure can be used to connect a CPU chip to a cluster of GPU chips. The CPU and GPU cluster can coherently read from and write to each other's memory. The...
Read More & Download | Provide Feedback | Share | Revision Date: 02/20/2018
Power ISAThe links below will take you to the Power Instruction Set Architecture (ISA) Version 2.07B and Power ISA Version 3.0B. POWER ISA v2.07B (for POWER8 & POWER8 with NVIDIA NVlink) POWER ISA v3.0B (for POWER9) POWER ISA v3.0C (for POWER9) Power ISA Version 2.07B consists of five books and a set of appendices. It is intended for use with IBM®...
Read More & Download | Provide Feedback | Share | Revision Date: 11/30/2015
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